`timescale 1ns / 1ps

module mod10_tb();

reg Clk;
reg Reset_n;
wire [3:0]Q;
wire clock;

defparam mod10_inst0.MCNT=24_999;

mod10 mod10_inst0(
.Clk(Clk),
.Reset_n(Reset_n),
.Q(Q),
.clock(clock)
);

initial Clk=0;
always #10 Clk=~Clk;

initial begin
Reset_n=0;
#201;
Reset_n=1;
#20000000;
$stop;
end

endmodule
